System to reduce latency for real time interrupts

ABSTRACT

A system for providing a time-based interrupt signal to a processor for executing a real time interrupt event with reduced interrupt latency, involves: a first programmable counter, which is capable of interrupting the processor by generating an interrupt signal on a regular time period based on the decrementing of an initial count value loaded therein, which value is re-loaded in the counter when the count is exhausted and the interrupt signal is generated; one or more second programmable counters, also having initial count values loaded therein that are decremented, and each of which, if the count is exhausted before that of the first counter, will not allow certain types of instructions or events, respectively associated with each second counter, to execute, if the execution of such instructions or events would cause an unwanted latency in the interrupt caused by the interrupt signal from the first counter.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to microprocessors and more particularlyto a method and means for eliminating unwanted latency in the executionof interrupt signals which produce regular time period interrupts thatallow tasks to be dispatched on a real-time periodic basis.

2. Problem to be Solved

In modern microprocessor systems, it is often necessary to provide theappearance of a real-time processor for certain system functions. Anexample is found in digital signal processor applications where there isa need for an interrupt mechanism for real time preemptive multi-taskingsince it is required that tasks be dispatched on a real-time periodicbasis. This is difficult to achieve due to the existence of certainfunctions that the microprocessor must perform that have unpredictableinterrupt latency.

In conventional microprocessor implementations, instructions areexecuted through a module of code performing architected events. Eachindividual instruction may require several machine or other clock cyclesto complete and the number of cycles required by each instruction mayvary due to complexity, amount of data handled, resource required,Virtual to Real address translation, Cache hit or miss, and such. Inmodern microprocessors, performance is improved by using various methodsthat reduce the apparent number of cycles needed to execute theinstructions, e.g., pipe-lining, branch guessing, out-of-orderexecution, multiple fetch and execution, etc. Further, outsideinfluences, such as memory utilization, I/O utilization, exceptionhandling, and the like, may cause a particular instruction to performdifferently at different times.

From the foregoing, it will be appreciated that complex events effectthe performance of an individual instruction as well as that of a module(group) of instructions. A problem is presented by this performancevariation in certain applications where it is required to provideinterrupt capability at precise intervals. With all the events effectingthe performance of a microprocessor instruction stream it is clear thatsome events may severely impact the interrupt latency, for instance,when an instruction has an outstanding memory request that it cannotcomplete until the memory operation has completed. If the memory is notavailable, e.g., when another microprocessor has the current Line in amulti-processor environment, the instruction could be delayed incompletion for a considerable time.

The functions that may add latency to an interrupt request beingserviced vary by implementation and by type. It is therefore desirablethat a system or mechanism be provided that eliminates the effect ofvarious machine functions on latency and that preferably is programmableso that a system implementer can adjust for his particular requirements.

Objects

It is accordingly an object of the present invention to provide a methodand means for eliminating the effect of various machine functions onlatency in executing interrupt requests.

It is a further object of the invention to provide a method and meanswhich eliminate the effect of various machine functions on latency inexecuting interrupt requests and which allow for programmability topermit adjustments for particular requirements.

SUMMARY OF THE INVENTION

The present invention involves a method and means that provide aprogrammable time-based interrupt which solves the latency problemthrough the use of the combination of a Real Time Interrupt Period(RTIP) register and one or more Safe Period Registers (SPRs) thatcontrol the execution of types or classes of events which must besuppressed in order to minimize the latency of servicing an interrupt ontime. In the preferred embodiment, the RTIP register is set up with aprogrammable count for defining the interrupt period. The content valueof the RTIP register determines the number of cycles, e.g., machine,processor, counter, or other clock iterations, until a Real TimeInterrupt Event (RTIE), and this value count is loaded into a counter,e.g., a decrementer, which, when its value is exhausted, i.e., is equalto "0" or goes negative, generates an RTIE signal. The decrementerdecrements on each machine or other clock cycle and the value of theRTIP register is re-loaded in the decrementer each time the decrementerreaches "0" and the RTIE signal is generated. In order to minimize thelatency of servicing the RTIE, a set of Safe Period Registers (SPRs) areused, each of which contains a programmable value for a type or class ofevents the execution of which must be suppressed in order to minimizethe latency of servicing an RTIE on time. The set of SPRs have thevalues of their contents loaded into decrementors that also decrement oneach clock cycle. When an SPR decremented value goes less than "0",before an RTIE signal is generated, the associated class of operation issuppressed, allowing the RTIE to be serviced on time. The suppression isended with the generation of the RTIE signal and the system recycles.

With this mechanism, a system programmer can set up the "Real Time"interrupt period in the RTIP register and set the SPR values such thatas the Real Time Interrupt Event approaches, each system function thatcould effect the interrupt latency is suppressed, as required, toguarantee that the Real Time interruption can take place on time.

Other means for creating the suppression signal(s) may involve having asingle counter (incrementer or decrementer) with registers containing acount value which, when surpassed by the counter, will assert thesuppression and/or interrupt signal(s). In a case wherein there arethree suppressible events, for instance, a count value is loaded intothe RTIP register representing the count value that will initiate a realtime interrupt, and each of the suppressible event counts is loaded intothe respective SPR with a count value that will initiate the respectivesafe period.

In systems with multiple Real Time Interruption requirements, the systemprogram can organize the RTIP register and the SPR's such that they arealways counting down for the next Real Time Interrupt Event.Alternatively, multiple RTIP and SPR registers can be implemented, eachprotecting a different Real Time Interrupt Event period.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagrammatic illustration that depicts the concepts of thepresent invention with two independent real time interrupt frequenciesor periods, P_(RTIP0) and P_(RTIP1).

FIG. 2 is a block diagram of a preferred hardware implementation of anRTIP register, RTIP0, and associated components in accordance with theinvention.

FIG. 3 is a block diagram of a hardware implementation of a real timeinterrupt mask and status register, RTIM, used in the invention.

FIG. 4 is a block diagram of a hardware implementation of a safe periodregister, SP0, of the invention.

FIG. 5 is a block diagram of a hardware implementation of a cyclecounter protection register SP3₋₋ DEC₋₋ REG and a time stampincrementer, TS₋₋ REG, of the invention.

FIG. 6 is a schematic of the logic circuitry which controls the realtime interrupt data flow in accordance with the invention, wherein:

FIG. 6a illustrates the control logic for the RTIP registers, the SPregisters, TS₋₋ REG, and RTIM update;

FIG. 6b illustrates the control logic for the enable signal to the SP3₋₋DEC₋₋ REG of FIG. 5; and

FIG. 6c illustrates the control logic for the SP registers and the RTIMregister signals in producing SUSPEND signals.

DETAILED DESCRIPTION OF THE INVENTION

Real time interrupt processing is accomplished in the preferredimplementation to be described by providing a means to divide real timeprocesses (P_(RT)) from non-real time processes (P_(NRT)). In order toaccomplish this, a real time interrupt frequency or period (P_(RTIP))must be established and maintained so that the real time interrupt willalways be processed in an exactly periodic fashion. The firstrequirement to be able to do this is that a counter be able to produce aknown, non-varying, periodic interrupt pulse. Further, the rate at whichthis real time interrupt frequency or period (RTIP) counter is updatedmust be able to be determined by software visible registers. It is alsoimperative that if this update rate changes, the real time operatingsystem be informed of this change.

The other difficulty in being able to provide a periodic interruptfrequency is the problem of controlling interrupt latency. Interruptlatency is the condition which results when a pending interrupt may notbe immediately serviced by its interrupt handler because the processoris busy finishing another previously started instruction. In order tocircumvent the problem of interrupt latency, the present invention firstgroups events which cause interrupt latency into three areas, thatis, 1) non-interruptable multicycle instructions, 2) non-real timesoftware disabling interrupts, and 3) non-interruptable instructionsfrom I/O devices on the external bus. Next, each of the three interruptlatency contributors are assigned a counter which is updated at the samerate that the real time interrupt frequency (RTIP) counter is updated.Each of the three counters are loaded by the real time operating systemwith values which guardband the worst case interrupt latency of itsparticular group and each disallows those events from occurring when thecounter reaches a criterion point, e.g., becomes negative, thusoperating as "safe period" registers (SPRs). By loading these "safeperiod" registers with values, P_(SP0), P_(SP1), and P_(SP2), takinginto account the start time of the next real time task, multiple realtime interrupt frequencies can be handled with just one set of safeperiod registers (SPRs), while still minimizing interrupt latency andmaximizing non-real time performance.

FIG. 1 depicts the foregoing concepts for two RTIP counters, RTIP0 andRTIP1, with two independent real time interrupt frequencies, P_(RTIP0)and P_(RTIP1). For P_(RTIP0) (the upper timing chart), there are threesafe period counters, SP0, SP1, and SP2. Each counter provides a safeperiod by suppressing a class of events when it's associated countdownto 0 occurs. The safe period is represented by the shaded area for eachsafe period counter (P_(SP0), P_(SP1), P_(SP2)). For P_(RTIP1) (thelower timing chart), the same function is supplied as for P_(RTIP0). Inthis example, there are two independent real time interrupt event (RTIE)hardware mechanisms RTIP0 and RTIP1. However, the same function could beachieved with one set of hardware. For example, the interrupt softwarecould keep track of the independent interrupt frequency requirement forRTIPO and RTIP1 and initialize the hardware for the next sequentialinterrupt event following the occurrence of the present interrupt event.

The preferred implementation has the ability to support up to fourindependent real time interrupt frequencies so that four RTIP registersmay be used. These registers may preferably be 32-bit registers,designated RTIP0-RTIP3. One register, RTIP0, of the four RTIP registersthat contain the values that will be decremented at the external busfrequency to create the real time interrupt period, is shown in FIG. 2.Other convenient clock frequencies may also be used in incrementing ordecrementing counters in the present implementation as may bealternatively selected by and will be within the purview of thoseskilled in the art. As seen in FIG. 2, an initializing signal, RTIP0₋₋EN, enables register RTIP0 by latching to load a 32-bit signal, RS₋₋REG₋₋ SRC1(31 . . . 0), from an external input bus, which input signalmay contain appropriate count data supplied to the RTIP0 register fromany of a number of general purpose registers within the processor. Thevalue count in 32-bit register RTIP0 is then loaded, under the controlof an RT0₋₋ DEC₋₋ MUX₋₋ CNTL signal through an appropriate multiplexer19, into a 32-bit real time interrupt period decrementer 20 whichdecrements the count, in cooperation with a decrement register 21, oneach processor cycle based on the external bus frequency. Decrementregister 21 feeds back a count signal RTIP0₋₋ DEC to multiplexer 20 andwhen the decremented RTIP register value becomes exhausted or goesnegative (MSB=1) then the real time interrupt period decrementer 20 getsreloaded from the RTIP0 register and continues to decrement. At the sametime a 32-bit real time interrupt signal RTIP0₋₋ S is generated by RTIP0and one bit thereof (31) is used in control logic (see FIG. 6a) inproducing a signal, RTIM₋₋ UPDATE, that is passed, through anappropriate multiplexer 29, to a real time interrupt mask (RTIM)register 30 (see FIG. 3). The input signal is masked and latched in RTIM30 and then various bits of the output signal RTIM₋₋ S are provided tothe interrupt priority logic, as shown in FIGS. 6a, 6b, and 6c. Alsowhen the decremented RTIP register value becomes negative, the contentsTS₋₋ REG₋₋ S of a time stamp incrementer TS₋₋ REG 50 (see FIG. 5), amonitonically increasing 32-bit counter which is updated at the externalbus frequency, is loaded (see FIG. 2) into a time stamp register TSR0,corresponding to the RTIP0 register, the decremented value of which wentnegative. There are four corresponding time stamp registers, in the formof 32-bit SPR's, denoted as TSR0-TSR3, for the four respective RTIPregisters, RTIP0-RTIP3.

Each of the four RTIP registers, RTIP0-RTIP3, has an associated set ofsafe period registers (SPRs) for the three interrupt latency problemareas identified as SP0, SP1, and SP2. In particular, the safe periodregister for multicycle instructions is a 32-bit SPR indicated as SP0(FIG. 4), the safe period register for software disabling interrupts isa 32-bit SPR indicated as SP1, and the safe period register for I/Oinstructions is a 32-bit SPR indicated as SP2. The contents of thesethree safe period SPRs are loaded from the input bus, in response to anenable signal, e.g., SP0₋₋ EN for SP0 (see FIG. 4), through appropriatemultiplexers 39, into respective decrementers 40 when a move to signal,e.g., MTSP0 from a general purpose register source, occurs (see FIG.6a). Each of the safe period registers, SP0, SP1, and SP2, has adecrementing register, e.g., SP0₋₋ DEC₋₋ REG, which operates in the samemanner as the RTIP decrementing register RT0₋₋ DEC₋₋ REG, and when theirdecremented values become negative they generate output signals, e.g.,SP0₋₋ S, a bit (31) of each of which is maskable via the RTIM register(see FIG. 6c), and produce respective suspend signals SUSPEND₋₋ MC,SUSPEND₋₋ INT, and SUSPEND₋₋ IO. These suspend signals then stop theappropriate instructions from being dispatched until the interrupt iscleared. They are cleared by the occurrence of any real time interruptfrom RTIP0-RTIP3.

In order to insure that real time tasks only use a predefined amount ofCPU resource, a mechanism is provided to generate an interrupt signal,SP3, after a programmable number of successfully dispatched cycles hasoccurred following the first return from interrupt (RFI) instructionafter writing to a cycle counter protection SPR, SP3₋₋ DEC₋₋ REG (seeFIGS. 5 and 6b). SP3₋₋ DEC₋₋ REG will be updated every internal CPUcycle in which at least one successful instruction is dispatched. Itshould be noted that dispatching an instruction does not mean that aninstruction has been successfully executed and completed. This mechanismwith the use of a microprocessor performance model can be used todetermine the correct value to load in SP3₋₋ DEC₋₋ REG to ensure thatthe real time task is protected in the time domain.

One additional interrupt can be generated in the real time interruptlogic shown in FIG. 6a. This interrupt will occur whenever the internalclock multiplication factor (CLKMF) changes. The change will be input toa real time clock RTI₋₋ CLK which provides an output to the RTIM₋₋UPDATE logic. The real time interrupt operating system will then have toquery other SPR's in the preferred implementation to determine what thepresent clock multiplication factor is and make any insectary updates.All of the registers, REG, in FIG. 6 are single bit latches that delaythe input signals by a single cycle.

It will accordingly be seen from the foregoing description taken withthe drawings that a system is disclosed using multiple programmablecounters for reducing latency time in executing computer instructions inresponse to interrupt or subroutine calls, and wherein memory withmultiple memory locations may be employed for storing the multipleprogrammable counters. All of the registers, except the DEC registersand TS₋₋ REG, are architected registers, i.e., they are visible to aprogrammer for loading and unloading program data.

The programmable count registers include at least one such register forasserting the interrupt at a predetermined time consistent with theprogrammable count, and at least one other such register for suppressingevents, as the interrupt time approaches, that may cause latency inresponding to the interrupt.

These programmable count registers are initialized using software bymeans of which a programmer may load the count registers withpredetermined values from memory each time a re-occurring programmableinterrupt period is needed. As an example, the program user may set therequired interrupt period into a first memory location. A program, aspart of it's interrupt servicing routine may fetch the first memorylocation and algorithmically, calculate the appropriate count values.The program would then load the count values into the count registers toinitiate a period of time after which, the hardware will interrupt theinterrupt handler. After starting the period of time, the interrupthandler will return control of the processor to other programs. Itshould be noted, that the interrupt handler needs only to calculate thecount values required once. The hardware, as described above,re-initializes the counts when they are exhausted such that theinterrupt handler doesn't have to spend time re-calculating and loadingcount values. It should also be noted that multiple real-time eventinterruption periods can be had by either replicating the count hardwareor having the interrupt handler, upon being interrupted, calculate theperiod required for the next to occur interrupt event.

What is claimed is:
 1. A system for providing a time-based interruptsignal to a processor for executing a real time interrupt event withreduced interrupt latency, comprising:first means for storing a firstcount value defining an interrupt period in terms of the number of countcycles until the time for executing a real time interrupt event; firstmeans for counting said count cycles and producing an interrupt signalwhen the cycle count reaches said number of count cycles defining aninterrupt period, said interrupt signal indicating the time forexecuting a real time interrupt event; second means for storing a secondcount value indicative of the number of count cycles until the time forexecuting a type or class of event which must be suppressed in order tominimize the latency of executing an associated real time interruptevent on time; second means for counting said count cycles and producingan indicative signal when the cycle count reaches said number of countcycles indicating the time for executing said type or class of event;and means, responsive to said interrupt signal and said indicativesignal, for suppressing the execution of any type or class of event tobe suppressed when an indicative signal occurs before an associatedinterrupt signal for indicating the time for executing said real timeinterrupt event.
 2. The system of claim 1 further comprising means forresetting said first and second means for counting each time aninterrupt signal is produced.
 3. The system of claim 1 wherein saidfirst means for storing comprises means for programming said first countvalue and said second means for storing comprises means for programmingsaid second count value.
 4. The system of claim 1 further comprising areal time interrupt mask (RTIM) register means for masking and latchingsaid interrupt signal.
 5. The system of claim 4 further comprising clockmeans for sensing a change in the internal clock multiplication factor(CLKMF) and producing an output signal indicative thereof to said RTIMregister means.
 6. The system of claim 1 further comprising:a time stampregister; a time stamp incrementer updated on each cycle count; andmeans, responsive to the cycle count exceeding said number of countcycles defining an interrupt period, for loading the contents of saidtime stamp incrementer into said time stamp register.
 7. The system ofclaim 1 further comprising: means for counting each count cycle at whicha successful instruction is dispatched; andmeans for generating aninterrupt signal after a programmable number of successfully dispatchedcycles has been counted by said counting means.
 8. Apparatus forproviding a programmable time-based interrupt signal to a processor withreduced interrupt latency, comprising:a Real Time Interrupt Period(RTIP) register means for storing a programmable count value defining aninterrupt period in terms of the number of counter iterations until thetime for executing a real time interrupt event; first decrementer means,responsive to said stored programmable count value, for decrementingsaid count value on each counter iteration and producing an interruptsignal, when the decremented count value is exhausted, indicating thetime for executing a real time interrupt event; first means forresetting said first decrementer means to decrement said count valueeach time said decremented count value is exhausted; at least one SafePeriod Register (SPR) means for storing a programmable count valueindicative of the number of counter iterations until the time forexecuting a type or class of event which must be suppressed in order tominimize the latency of executing an associated real time interruptevent on time; second decrementer means, responsive to said storedprogrammable count value in said SPR means, for decrementing said countvalue and producing an indicative signal when the decremented countvalue is exhausted indicating the time for executing said type or classof event which must be suppressed; second means for resetting saidsecond decrementer means to decrement said count value each time saiddecremented count value is exhausted; and means, responsive to saidinterrupt and said indicative signals, for suppressing the execution ofany type or class of event to be suppressed when an indicative signaloccurs before an associated interrupt signal.
 9. Apparatus as in claim 8further comprising a real time interrupt mask (RTIM) register means formasking and latching said interrupt signal.
 10. Apparatus as in claim 8further comprising:a time stamp register; a time stamp incrementerupdated on each counter iteration; and means, responsive to thedecremented RTIP register means count value becoming negative, forloading the contents of said time stamp incrementer into said time stampregister.
 11. Apparatus as in claim 8 further comprising:means forcounting each counter iteration at which a successful instruction isdispatched; and means for generating an interrupt signal after aprogrammable number of successfully dispatched cycles has been countedby said counting means.
 12. A method for providing a programmabletime-based interrupt signal to a processor for executing a real timeinterrupt event with reduced interrupt latency, comprising the stepsof:storing a first count value defining an interrupt period in terms ofa number of clock cycles until the execution of a real time interruptevent; decrementing said first count value on each clock cycle andproducing an interrupt signal when the decremented value reaches aminimum indicating the time for the execution of a real time interruptevent; storing a second count value indicative of a number of clockcycles until the execution of a type or class of event which must besuppressed in order to minimize the latency of executing an associatedreal time interrupt event on time; decrementing said second count valueon each clock cycle and producing an indicative signal when thedecremented value reaches a minimum indicating the time for executingsaid type or class of event which must be suppressed; and sensing saidinterrupt and said indicative signals and suppressing the execution ofany type or class of event to be suppressed when an indicative signaloccurs before an associated interrupt signal.
 13. The method of claim 12wherein said first count value is programmable.
 14. The method of claim12 wherein said second count value is programmable.
 15. The method ofclaim 12 further comprising the steps of repeating the decrementing ofsaid first count value each time an interrupt signal is produced, andrepeating the decrementing of said second count value each time anindicative signal is produced.
 16. The method of claim 12 wherein saidtype or class of event which must be suppressed comprisesnon-interruptable multicycle instructions.
 17. The method of claim 12wherein said type or class of event which must be suppressed comprisesnon-real time software disabling interrupts.
 18. The method of claim 12wherein said type or class of event which must be suppressed comprisesnon-interruptable instructions from I/O devices on the external bus. 19.A system for providing a time-based interrupt signal to a processor forexecuting a real time interrupt event with reduced interrupt latency,comprising:memory means for storing a first count value defining a timeperiod, in terms of clock cycles, for the execution of a real timeinterrupt event; means, responsive to said clock cycles, for producing atime-based interrrupt signal when said first count value time periodpasses; memory means for storing a second count value defining a timeperiod, in terms of clock cycles, for the execution of operations of aselected class; means, responsive to said clock cycles, for producing anoperations signal when said second count value time period passes; andmeans, responsive to said interrupt signal and said operations signal,for producing a signal suppressing the execution of operations of theselected class until said time-based interrupt signal is sent to theprocessor for the execution of a real time interrupt event, when saidoperations signal is defined to occur before said interrupt signal. 20.The system of claim 19 further comprising:a real time interrupt mask(RTIM) register means for masking and latching said interrupt signal;and clock means for sensing a change in the internal clockmultiplication factor (CLKMF) and producing an output signal indicativethereof to said RTIM register means.